Embodiments of the present disclosure relate to a burst length control circuit and a semiconductor device including the same, and more particularly, to a technology capable of controlling a burst length in a low power semiconductor memory device.
Semiconductor memory devices have been developed with increased degrees of integration and operating speeds. To increase operating speeds, synchronous memory devices capable of operating in synchronization with an external clock have been disclosed.
First developed were single data rate (SDR) synchronous memory devices in which one bit of data is inputted or outputted through one data pin during one cycle of an external clock, in synchronization with a rising edge of the external clock.
However, SDR synchronous memory devices had insufficient speed for a system configured to perform high speed operations. Accordingly, double data rate (DDR) synchronous memory devices configured to transfer two bits of data during one cycle of a clock have been introduced.
In the DDR synchronous memory devices, a first bit and a second bit of data are consecutively inputted or outputted through each data input/output (I/O) pin, the first and second bits in synchronization with a rising edge and a falling edge of a supplied external clock, respectively. Therefore, since a bandwidth at least two times greater than the conventional SDR synchronous memory device may be realized without increasing a frequency of the external clock, a high speed operation may be correspondingly achieved.
DDR synchronous memory devices use a multi-bit prefetch scheme in which multiple bits are internally processed at a time. The multi-bit prefetch scheme refers to a scheme in which data sequentially inputted are arranged in parallel in synchronization with a data strobe signal and then the parallelized multi-bit data are simultaneously stored in a memory cell array by a write command which is inputted in synchronization with an external clock signal.
DDR synchronous memory devices may include a plus mode capable of supporting two concurrent operations in different bank groups. If a DDR synchronous memory device enters the plus mode, when considering DDR3, write/read operations may be initiated that use two clock cycles during the plus mode, in contrast to four clock cycles used by analogous operations during a normal (non-plus) mode.
The plus mode may be used in an on-the-fly mode. An on-the-fly mode is a mode for determining whether to use a first burst length (e.g., BL4) or a second burst length (e.g., BL8) according to a bit in an address of a write or read command.
As prescribed in the JEDEC DDR3 standard, in order to utilize all cells in memory banks in a first burst length BL4 or an on-the-fly mode operation, banks are generally divided into two bank groups, e.g., first and second bank groups, and an operation for selecting whether to write data in the first or the second bank group is performed.
When a memory device is operating in a normal on-the-fly mode, an operation using four clock cycles is performed, and an address change is performed during four clock cycles. When operating in a plus on-the-fly mode, because an operation in a single clock cycle is required, an address toggle associated with the on-the-fly operation may be performed.
A conventional product under Low Power DDR3 (LPDDR3) may adopt a burst length chop scheme in which a burst length BL×2 mode is modified to have the timing of a burst length BL×1 mode by a burst stop termination (BST) command.
However, in the burst stop termination (BST) scheme, a received command signal may be counted, which may be inconvenient. For example, in order to realize a burst length BL16 in a burst length BL32 mode, a burst stop termination command may be counted.
Further, in the related art, if a burst stop termination signal is received by a write control unit and a read control unit, the magnitude of a burst length is changed according to strobe signals of the write control unit and the read control unit. As a result, an auto-precharge mode is disabled when using the conventional burst stop termination (BST) scheme.